Doping of copper wiring structures in back end of line processing

ABSTRACT

A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

DOMESTIC PRIORITY

This application is a continuation of U.S. patent application Ser. No.14/274,962, filed May 12, 2014, which is a divisional application ofU.S. patent application Ser. No. 13/599,256, filed Aug. 30, 2012, nowU.S. Pat. No. 8,765,602, the disclosure of which is incorporated byreference herein in its entirety.

BACKGROUND

The present disclosure relates generally to semiconductor devicemanufacturing techniques and, more particularly, to doping of copperwiring structures in back end of line (BEOL) processing.

Integrated circuits are typically fabricated with multiple levels ofpatterned metallization lines, which are electrically separated from oneanother by interlayer dielectrics containing vias at selected locations,to provide electrical connections between levels of the patternedmetallization lines. In recent years, copper (Cu) has replaced aluminum(Al) as the metal of choice for wiring of microelectronic devices, suchas microprocessors and memories. However, copper has a tendency todiffuse through insulators, such as silicon dioxide, during hightemperature processes. As a result, the use of copper wiring alsonecessitates the placement of efficient diffusion barriers surroundingthe copper wires, thereby keeping the copper atoms confined to theintended wiring locations and preventing circuit malfunctions, such asshorts.

As electronic devices become smaller, there is also a continuing desirein the electronics industry to increase the circuit density inelectronic components, e.g., integrated circuits, circuit boards,multi-chip modules, chip test devices, and the like, without degradingelectrical performance, e.g., without introducing cross-talk capacitivecoupling between wires while at the same time increasing speed or signalpropagation of these components. One method for accomplishing thesegoals is to reduce the dielectric constant of the dielectric material inwhich the wires are embedded. Toward this end, a new class of lowdielectric constant (low-K) materials has been created. Low-K interleveldielectric (ILD) materials are advantageous so long as devicereliability is not compromised. However, the lower the dielectricconstant of the low-K dielectric material, the more challenging theintegration becomes. For example, low-K generally corresponds to lowermodulus, lower thermal conductivity, increased porosity, and greatersusceptibility to plasma damage, in turn leading to lower reliability.

SUMMARY

In an exemplary embodiment, a method of forming a metal interconnectstructure includes forming a copper line within an interlevel dielectric(ILD) layer; directly doping a top surface of the copper line with acopper alloy material; and forming a dielectric layer over the ILD layerand the copper alloy material; wherein the copper alloy material servesan adhesion interface layer between the copper line and the dielectriclayer.

In another embodiment, a method of forming a metal interconnectstructure includes forming an opening within an interlevel dielectric(ILD) layer; forming a first seed layer in the opening; forming a copperlayer in the opening over the first seed layer; planarizing the copperlayer and the first seed layer so as to define a copper line; directlydoping a top surface of the copper line with a copper alloy material;and forming a dielectric layer over the ILD layer and the copper alloymaterial; wherein the copper alloy material serves an adhesion interfacelayer between the copper line and the dielectric layer.

In another embodiment, a metal interconnect structure includes a copperline formed within an interlevel dielectric (ILD) layer; a barrier layersurrounding bottom and sidewall surfaces of the copper line; a topsurface of the copper line directly doped with a copper alloy material;and a dielectric layer formed over the ILD layer and the copper alloymaterial; wherein the copper alloy material serves an adhesion interfacelayer between the copper line and the dielectric layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring to the exemplary drawings wherein like elements are numberedalike in the several Figures:

FIG. 1 is a scanning electron microscope (SEM) image illustratingdelamination of an NBLoK insulating layer from a lower copper wiringline;

FIG. 2 is an enlarged image of a portion of FIG. 1, illustratingdelamination of an NBLoK insulating layer;

FIGS. 3 through 6 are a series of cross-sectional views illustrating amethod of doping the top surface of the copper line with a metal dopant,in which:

FIG. 3 illustrates an ILD layer having a wiring opening patternedtherein, and a high doped seed layer formed over the top surface of theILD layer;

FIG. 4 illustrates a copper layer electroplated over the seed layer ofFIG. 3;

FIG. 5 illustrates chemical mechanical planarization or polishing (CMP)of the excess copper layer and seed layer of FIG. 4;

FIG. 6 illustrates a layer of NBLoK formed over the layer and the copperlayer of FIG. 5, resulting in diffusion of the dopant species from theseed layer into the copper layer;

FIGS. 7 through 12 are a series of cross-sectional views illustrating amethod of a metal interconnect structure by doping the top surface ofthe copper line with a metal dopant, in accordance with an exemplaryembodiment, in which:

FIG. 7 illustrates an ILD layer having a wiring opening patternedtherein, and a high doped seed layer formed over the top surface of theILD layer;

FIG. 8 illustrates a copper layer electroplated over the seed layer ofFIG. 7;

FIG. 9 illustrates CMP of the excess copper layer and seed layer of FIG.8;

FIG. 10 illustrates the formation of a high doped seed layer over theILD layer, low concentration seed layer, and copper layer of FIG. 9;

FIG. 11 illustrates an anneal of the device of FIG. 10 so as to drivedopant atoms into the top surface of the copper layer, creating a dopedregion;

FIG. 12 illustrates removal of the high concentration seed layer of FIG.11 and deposition of a NBLoK layer;

FIGS. 13 through 16 are a series of cross-sectional views illustratingan alternative embodiment of FIGS. 9 through 12, in which:

FIG. 13 illustrates CMP of the excess copper layer and seed layer ofFIG. 8, wherein the copper layer and seed layer are recessed below theILD layer;

FIG. 14 illustrates the formation of a high doped seed layer over theILD layer, low concentration seed layer, and copper layer of FIG. 13;

FIG. 15 illustrates planarization of the portion of the high doped seedlayer over the ILD layer of FIG. 14, leaving the high doped seed layer,and an anneal to drive dopant atoms into the top surface of the copperlayer, creating a doped region;

FIG. 16 illustrates deposition of a NBLoK layer over the device of FIG.15;

FIGS. 17 and 18 are cross-sectional views illustrating an alternativeembodiment of FIGS. 15 and 16, in which:

FIG. 17 illustrates planarization of the portion of the high doped seedlayer over the ILD layer of FIG. 14, leaving the high doped seed layer;and

FIG. 18 illustrates deposition of an NBLoK layer over the device of FIG.17.

DETAILED DESCRIPTION

FIG. 1 is a scanning electron microscope (SEM) image illustratingdelamination of an NBLoK insulating layer from a lower copper wiringline. As illustrated in FIG. 1, the lower copper wiring line 102 has alayer of NBLoK dielectric 104 formed thereupon. The lower copper wiringline 102 is intended to be electrically connected to an upper copperwiring line 106 by vias 108. However, as will be noted, due to the weakNBLoK adhesion to copper, delamination of the NBLoK dielectric 104 fromthe top surface of the lower copper wiring line 102 has also causedseparation of the vias from the lower copper wiring line 102, in turnleading to device opens. This delamination is also more clearly depictedin the enlarged image of FIG. 2.

Adhesion between the copper lines and NBLoK can be greatly enhanced bydoping the top surface of the copper line with a heavy noble metal, suchas manganese (Mn). One possible manner of locating the Mn at the topsurface is by using a copper manganese (CuMn) seed layer prior to copperplating, and thereafter thermally diffusing the Mn through the copperline up to the top surface, as illustrated in FIGS. 3-6.

As particularly shown in FIG. 3, an interlevel dielectric (ILD) layer302 (e.g., oxide, nitride, low-k dielectrics, etc.) has a wiring opening304 patterned therein, in accordance with damascene processingtechniques. A seed layer 306 is formed over the top surface of the ILDlayer 302, as well as over sidewall and bottom surfaces of the opening304 in preparation for copper material plating. Although notspecifically illustrated in FIG. 3, one skilled in the art willappreciate one or more barrier layers (e.g., tantalum, titanium based)may be formed over the ILD layer 302 prior to seed layer deposition.

In the example depicted, the seed layer 306 includes a CuMn alloy havinga manganese dopant concentration of about 2% atomic. Notably, such aconcentration is higher than typically may be used in conjunction with aCuMn seed layer for electromigration prevention purposes. In the lattercase, such a seed layer concentration may only be on the order of about0.5% atomic. Generally speaking, electromigration concerns are moreprevalent for the smaller thicknesses of wiring on the lower levels.However, CuMn seed concentrations higher than about 0.5% atomic on theselevels may have the disadvantage of significantly increasing lineresistance. It will be noted that other metal materials may also be usedfor dopant alloy materials such as, for example, cobalt (Co), ruthenium(Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium(Ir), platinum (Pt), and gold (Au).

In FIG. 4, a copper layer 308 is electroplated over the seed layer 306so as to completely overfill the opening. This is followed by chemicalmechanical planarization or polishing (CMP) of the excess copper layer308 and seed layer 306 (and barrier layer) to expose the top surface ofthe ILD layer 302, as shown in FIG. 5. Then, as shown in FIG. 6, a layerof NBLoK 310 is formed over the ILD layer 302 and the copper layer 308.The deposition occurs at an elevated temperature of about 400° C.,resulting in diffusion of the Mn species from the seed layer 306 intothe copper layer 308. Those Mn atoms which diffuse to the top surface ofthe copper layer 308 are depicted by region 312 in FIG. 6, wherein thedoped region 312 is intended to promote a better adhesion interfacebetween the copper layer 308 and the NBLoK layer 310. Layer 302, in apreferred embodiment is NBLoK, but can be any dielectric layer whichinhibits copper diffusion.

One difficulty, however, with a seed layer/diffusion approach to topsurface doping is relatively large thickness (e.g., about 3 micron (μm))of copper line the dopant atoms must travel to reach the surface. As aresult, the doping levels of the Mn at the doped region 312 arerelatively low, which ultimately limits the adhesion benefit of the Mn.In other words, it is difficult to get enough Mn through the thickcopper lines to reach the top surface where it is beneficial foradhesion. In addition, the increase in Mn concentration at the seedlayer will increase the line resistance of the copper lines, as comparedto lines having a lower CuMn seed layer concentration, or lines havingonly a Cu seed layer. Moreover, diffusion through the entire linestructure also leads to larger variability in the line resistancesthemselves.

Accordingly, FIGS. 7 through 12 are a series of cross-sectional viewsillustrating a method of forming a metal interconnect structure bydoping the top surface of a copper line with a metal dopant, inaccordance with an exemplary embodiment. The exemplary embodimentimproves NBLoK-to-copper adhesion by directly doping the top surface ofthe copper lines with up to 2% CuMn (or other suitable copper alloymaterial). Specifically, an exemplary embodiment involves doping the topsurface of the copper lines with an dopant material such as Mn bysputtering CuMn directly on the top surface of the copper lines,thermally driving the Mn into the copper surface, and thereafterremoving the sputtered CuMn with a touch-up CMP step.

In comparison with the previously described technique, FIG. 7illustrates an ILD layer 302 (e.g., oxide, nitride, etc.) having awiring opening 304 patterned therein, in accordance with damasceneprocessing techniques. A seed layer 314 is formed over the top surfaceof the ILD layer 302, as well as over sidewall and bottom surfaces ofthe opening 304 in preparation for copper material plating. However,whereas the seed layer 306 of FIG. 3 has the increased 2% CuMnconcentration, the seed layer 314 may have a low CuMn concentration ofabout 0.5% atomic Mn, or perhaps no dopant material at all. In FIG. 8, acopper layer 308 is electroplated over the seed layer 314 so as tocompletely overfill the opening. This is followed by CMP of the excesscopper layer 308 and seed layer 314 (and barrier layer, not shown), asshown in FIG. 9.

Then, as shown in FIG. 10, a high concentration CuMn seed layer 316(e.g., 2% atomic Mn) is formed over the ILD layer 302, low concentrationCuMn seed layer 314, and copper layer 308. The seed layer 316 may beformed by sputtering, for example. An anneal is then performed so as todrive Mn atoms into the top surface of the copper layer, creating adoped region 312 as shown in FIG. 11. The sputtered high concentrationCuMn seed layer 316 is then removed such as by CMP, leaving the dopedregion 312 as an interface for better adhesion of NBLoK. The depositionof the NBLoK layer 310 is illustrated in FIG. 12.

In an alternative embodiment, following the processing shown in FIG. 8,the copper layer 308 and seed layer 314 may be further recessed belowthe top surface of the ILD layer 302, such as by intentional dishing(over-polish) during CMP or by a separate wet etch step to create arecess 318 as shown in FIG. 13. The recess 318 may be on the order ofabout 0.2 μm in depth, for example. Then, as shown in FIG. 14, a highconcentration CuMn seed layer 316 (e.g., 2% atomic Mn) is formed overthe ILD layer 302, low concentration CuMn seed layer 314, and copperlayer 308. Again, the seed layer 316 may be formed by sputtering, forexample. In one embodiment, an anneal may then be performed as describedabove so as to drive Mn atoms into the top surface of the copper layer,creating a doped region 312.

As shown in FIG. 15, the portions of the high concentration CuMn seedlayer 316 atop the ILD layer 302 may be removed by CMP, leaving aportion of the high concentration CuMn seed layer 316 over the lowconcentration CuMn seed layer 314 and copper layer 308. As such, thecombination of the doped region 312 and remaining high concentrationCuMn seed layer 316 provide an interface for better adhesion of NBLoK byensuring high Mn doping (˜2%) on this surface. The deposition of theNBLoK layer 310 is illustrated in FIG. 16.

In still another embodiment, because of the recessing in FIG. 13, whichleaves a portion of the high concentration CuMn seed layer 316 atop thelow concentration CuMn seed layer 314 and copper layer 308, an annealneed not be performed. That is, as shown in FIG. 17, the sputtered highconcentration CuMn seed layer 316 atop the low concentration CuMn seedlayer 314 and copper layer 308 serves as the interface for thesubsequently deposited NBLoK layer. The deposition of the NBLoK layer310 is illustrated in FIG. 18.

As discussed above, prior to forming a low concentration CuMn seed layeror perhaps a Cu seed layer in a patterned opening, a diffusion barrierlayer is typically formed prior to seed layer deposition. It will benoted that a similar barrier layer(s) may also be formed prior todeposition of the high concentration CuMn seed layer 316.

While the disclosure has been described with reference to a preferredembodiment or embodiments, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedfor elements thereof without departing from the scope of the disclosure.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the disclosure withoutdeparting from the essential scope thereof. Therefore, it is intendedthat the disclosure not be limited to the particular embodimentdisclosed as the best mode contemplated for carrying out thisdisclosure, but that the disclosure will include all embodiments fallingwithin the scope of the appended claims.

What is claimed is:
 1. A metal interconnect structure, comprising: acopper line formed within an interlevel dielectric (ILD) layer; abarrier layer surrounding bottom and sidewall surfaces of the copperline, with a sidewall of the copper line having a sidewall copper alloyconcentration; a top surface of the copper line directly doped with acopper alloy material, the top surface of the copper line having a topcopper alloy concentration; wherein the top copper alloy concentrationis greater than the sidewall copper alloy concentration; and adielectric layer formed over the ILD layer and the copper alloymaterial.
 2. The structure of claim 1, wherein: the copper alloymaterial comprises a doped region of CuMn having a manganeseconcentration of greater than 0.5% atomic; and the dielectric layercomprises an NBLoK (SiC(N,H)) layer.
 3. The structure of claim 1,wherein the copper line has a thickness of about 3 microns (μm).
 4. Thestructure of claim 1, wherein: the top surface of the copper line isdirectly doped with a copper alloy material comprising a highconcentration CuMn seed layer having a manganese concentration of about2.0% atomic; and the dielectric layer comprises NBLoK (SiC(N,H)).
 5. Thestructure of claim 4, wherein the copper line is formed on a lowconcentration CuMn seed layer having a manganese concentration of about0.5% atomic or less.